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Problems and Promises with SMT-BGA-BTC in a Sn-Pb & LF World

  • Test your understanding of SMT with the questions below. If you have trouble answering some of the questions, you may benefit from courses taught by Mr. Ray Prasad.




    1.  For what do the following acronyms stand?

    BGA and BTC COB





    2.  Indicate which of the SMT board Types (I, II, III) typicallymakes use of each of the following components and processes: (circle as manyas apply)

    Wave soldering:

    Type I  Type II  Type III

    Reflow soldering

    Type I  Type II  Type III

    Leaded SMT components

    Type I  Type II  Type III

    Leadless Resistors/Caps

    Type I  Type II  Type III

    THMT components

    Type I  Type II  Type III

    Adhesive attachment

    Type I  Type II  Type III

    Solder paste

    Type I  Type II  Type III

    3.  A manufacturing facility has the capability of producing Type II SMT assemblies.  What additional equipment is necessary to produce Type I assemblies?

    4.  Another manufacturing facility has full THMT production capability plus a pick-and- place machine (with adhesive dispensing), and an infrared oven.  What SMT assembly types is it capable of producing?

    5.  On a Type II board, which are placed first on the primary side: SMT devices or THMT

    devices?  Why?

    6.  What is the PRIMARY function of the adhesive used in Type II and III assembly?

    7.  What are some of the reasons that will keep us in through hole technology for some time to come?

    8.  Which way should the colored side a chip resistor face? Why?

    9.  What does the resistor designation1206 mean? and 1825? What about resistor and capacitor designations 0201 and 1005?

    10. What is the difference between Japanese (EIAJ)and American (JEDEC)standard fine pitch packages?

    11. Is there one particular lead configuration better than other? Why? Which direction are we headed?  What is lead coplanarity requirement for component? Is it different for BGA?

    12. List at least five major features of a Pick and Place Machine.

    13. What determines through put? Pick and place or Screen printer?

    14. Which plays a greater role in overall level of defect? Choose one - Pick and place, screen printer, reflow oven

    15. What are the major requirements for a screen printer?

    16. What are major requirements for a reflow oven?

    17. What is the maximum variation on the same joint on the same board on the same day can be expected?

    18. What determines solder joint reliability in PCAs? a)height of solder joint, b)pitch of leads?

    19. Name some of the advanced packaging technologies

    20. Where and why does flip chip technology really make sense?

    21. Why and when do you need to consider MCM?

    22. What are the differences between CBGA balls and PBGA balls?

    23. When and why do you use CCGA? What are the disadvantages of CCGAs?

    24. What are the benefits of BTC/MLF/QFN packages?

    25. What are the key concerns of BTC/MLF/QFN Packages?

    26. What are the concerns of vias in QFN thermal/ground plane? What are the ways to alleviate those concerns? What is the most effective method?


    1.  DFM is the key to high yield.  If the board is designed for manufacturing, any manufacturing house can achieve the same yield.  True/False

    2.  Which are of DFM is affected by Lead Free? A)Laminate b)Component c)Surface Finish d)moisture sensitivity, e)land pattern, e)inter-package spacing f)Stencil design. List them.

    3.  Why does every company need its own unique internal DFM document? Which industry document is a good starting point? Why is that document not adequate?

    4.  What are the pros and cons of HASL, OSP and ENIG surface finishes?

    5.  The selection of surface finish should be made by taking into account the type of flux being used and whether or not nitrogen is used. True or False?

    6.  What is one thing that can be done to prevent corrosion of Immersion surface finish in sulfurous or salty environments

    7.  What causes plastic package cracking?  List some of the MAJOR contributing factors.

    8.  Moisture sensitive packages, if not dry when subjected to reflow, can cause : Check all that apply: a)part movement, b)package cracking, c)bridging, d)other

    9.  How can plastic package cracking be prevented?  Is there an industry standard available?  If yes, please list their names.

    10.  Why is moisture-induced package cracking  NOT a problem for plastic DIPs?  Why is it even a bigger problem for BGA?

    11.  How would you ensure that moisture sensitive packages that have exceeded their exposure limit are not used?

    12.  What is the main cause of black pad? In which surface finish?

    13.  What is the main cause of planar micro-via void? In which surface finish?

    14.  What is the main concern in OSP surface finish?

    15.  Why is bismuth allowed in component lead surface finish even though it may be potentially harmful if mixed with lead?

    16.  How does hole size and layer count affect the cost of PCB?  Why?

    17.  What are the major cost drivers in Printed Boards?

    18.  What are the causes of bridging in SOIC when wave soldering?

    19.  How do you prevent opens in reflowed fine pitch leads during wave soldering?

    20.  Is via in pad design acceptable? When and why? When and why not?

    21.  Of all the DFM rules and guidelines, which one is the most critical DFM rule?

    22.  Of all the factors that require higher inter-package spacing, which one among them is the key driver for minimum spacing?

    23.  What might the impact be of violating interpackage spacing rules?

    24.  Interpackage spacing rules are dependent of the soldering method used (wave solder or reflow solder)True/False

    25.  Interpackage spacing rules related to auto-placement, test, and rework.  True/False

    26.  What is the orientation of SOIC during wave soldering?

    27.  Please list the surface mount components that can be wave soldered?

    28.  What is the spacing for capped and uncapped vias?

    29.  Via in Padis generally not a common practice for reflow.  Why?

    30.  Why and where via in pad design is becoming a necessary? What are the consequences of it?

    31.  Why is it necessary to cap vias under fine pitch and BGAs if the board goes through wave soldering?

    32.  In a mixed Type II assembly, why do fine pitch solder joints open up after reflow even when they had acceptable solder joints during reflow?

    33.  What are the common causes of voids?

    34.  What is the main impact of BGA on board design?

    35.  What is the impacts poor land pattern design?

    36.  What are the main problems (difficulties)in designing land pattern design?

    37.  Why should the land pattern length be longer for capacitor than resistor even though they are the same size?

    38.  In chip component pad design, which is important? Pad width or pad length?

    39.  What are the main causes of tombstoning?

    40.  What is the one thing in pad design that you can do to minimize component shift, draw- bridge, and tombstoning during reflow?

    41.  Which fillet is important for gull wing leads? And for J type leads?

    42.  How can you prevent MELFs from rolling off during reflow?

    43.  Which is the preferred design approach for BGA- NSDM or SMD pad? Why?

    44.  What are some of the common defects caused by poor land pattern design?

    45.  For a given component, if both wave and reflow soldering can process it, is it a good idea to use the same pad designs for both processes?If yes, Why? If not, why?

    46.  What is the reason for non-soldermask defined pad for BGA?

    47.  Should the aperture for stencil be bigger or smaller than the pad?  Why?  When is the reverse true?

    48.  In general is the reliability of SAC solders better or worse than tin-lead reliability?

    49.  Is pad cratering better or worse with lead free BGA than tin-lead BGA? Why?

    50.  Is shock and drop of SAC solders better or worse than tin-lead solders? Why? What changes is it causing in alloy selection for mobile products?

    51.  What are the concerns of QFN on solder joint reliability? Why?

    52.  What is the best way to design land pattern for QFN with pull back and no pull back leads?

    53.  What is the best way to design stencil for QFN to prevent QFN floating and minimize voids?  But what problem does this create?


    1.  How is adhesive applied to the board? What type of process is used to cure adhesive?

    2.  Does it take less time to cure adhesive in a 10-zone oven than a 4-zone oven?

    3.  What defects are caused by excess adhesive? Insufficient adhesives?

    4.  What are consequences of not controlling the temperature ramp rate during adhesive cure?

    5.  Which has most impact on cure strength during adhesive cure: cure temperature or cure time?

    6.  What is the minimum cure strength needed to ensure that bottom side components do not fall off during wave soldering

    7.  What is the composition of the most widely used solder in the electronics industry? At what temperature does the solder melt?

    8.  What is the difference between solidus and liquidus point? Which temperature is important for determining peak reflow temperature

    9.  List some of the common causes of solder balls?

    10. What is the size distribution of solder paste powder particles if there are no fine pitch components on the board? Why is it necessary to change this size distribution for fine pitch technology?

    11. Why is it necessary to bring solder paste and adhesive to room temperature before use?

    12. Which is going to be less of a concern if there is misprinting/misplacement – misprinting along the sides of chip component pads or along the lengths of chip component pads? Why?

    13. Which is most widely used in the industry - Stencils or Screens? Why?  Metal Squeegee or Rubber squeegee?  Why?

    14. What is the recommended aspect ratio for stencil aperture design? And recommended area ratio? What is the main reason?

    15. What is the ratio of aperture width to solder power size to prevent clogging?

    16. What are some of the key features of etched, laser cut and electroformed stencils?

    17. Should the stencil aperture be smaller or larger than pad? Why? Give an example where the reverse is true.

    18. What is the minimum solder volume requirement for CBGA?

    19. What is the common stencil aperture design practice for QFNs? Why?

    20. What are the two main consequence of too much paste for QFN? And the consequences of too little paste?

    21. What percentage coverage is generally required at QFN ground/thermal plane site?

    22. Why solder volume is not so critical for PBGA? But why and when is it preferable to use paste and not only flux for PBGA?

    23. How would you prevent solder beads or “squeez balls” (large solder balls trapped under chip components)?

    24. What are the standards for solderability test? Please list their numbers?

    25. How is dewetting differentiated from non-wetting? List the names of industry solderability specs

    .26. What would you do differently if you are having insufficient hole fill in through hole joints during wave soldering?  What is the minimum hole fill requirement?

    27. Can only one solder profile be used for all products when using forced convection IR?

    28. How should thermal profile be developed?

    29. True or false: Reflow profile is solder paste flux dependent. Why?

    30. True or false: Each product needs its own unique profile. Why?

    31. What are the pros and cons of “long soak to peak” and “ramp to peak” profiles?

    32. In developing solder profile for BGA, what is critical requirement and how is it achieved?

    33. What is superheat? What is the recommended superheat for Sn-Pb eutectic solder? And for lead free solder?

    34. When can the Cu-Sn solders with or without Ni/Ge are used for reflow and when they should not? Why?

    35. What is backward compatibility? And forward compatibility?

    36. What are the concerns in backward and forward compatibility scenarios?

    37. How does laser address backward compatibility soldering concerns?

    38. What is the recommended profile for backward compatibility?

    39. What are some of the major problems in wave soldering?

    40. If the board were designed for wave soldering, what would be the cause of bridging in SOIC during wave soldering?

    41. What are the benefits of N2? Can design and process problems be avoided by the use of Nitrogen?

    42. What causes ceramic capacitor cracking?

    43. What are the options for selective soldering of surface mount components?

    44. What is one process that prevents the need for selective soldering of through hole components?

    45. When does it make sense to use paste in hole process?  What are some of the concerns of paste in hole process?

    46. In calculating the paste volume needed for paste in hole process, do we take into account for the paste pushed in the hole during printing?

    47. When paste in hole process is not feasible?

    48. What does "SIR" stand for and what is a SIR Test Pattern? On what Types of boards must SIR test patterns be placed? On what side(s)of those boards?

    49. What are some of the key issues with “No Clean” flux and pastes?What are the three methods of cleanliness measurements?

    50. What are some of the problems in cleaning fine pitch components?

    51. How does BGA solve some of the problems of fine pitch?  What new problems does it create?

    52. What is “smiling” or “head-in-pillow”BGA problem?  What is “frowning” BGA


    53. What kind of manufacturing defect can be caused by “smiling” BGA?

    54. What kind of manufacturing defect is caused by “frowning” BGA?

    55. List two things you need to do to prevent opens in BGAs during wave soldering.

    56. What are the causes of voids in BGAs?  What are the acceptable limits? 

    57. True or False: The accept/reject criteria in IPC 610 for voids is for Process related voids only

    .58. The location of the void is more important than its size.  True/False and why?

    59. List some of the common inspection methods

    60. Why do we need overlapping inspection methods?

    61. What is preferable? Bridge or an open? Why?  What is the recommended ratio of bridge to open?

    62. What are the concerns in rework? A)Board warpage, B)melting of solder joints of adjacent components, C)Sufficient spacing between packages, D)Other  

    63. What is the key concern in rework of through hole components? Why? Why is that not a concern during wave soldering? What are some of the options to mitigate this concern?

    64. What are the pros and cons of laser and hot air rework?

    65. List the names of industry workmanship standards?

    D: Questions on Causes of Defects

    1.  What are three major areas for the root cause of defects?

    2.  Are there times when there could be more than one cause for the same defect?

    3.  What are the types of defects that could be caused if you clean stencil by hand wiping only?

    4.  What is one reason that causes both no solder or too much solder in chip components during wave soldering?

    5.  If board is designed correctly for wave soldering (orientation, pad size etc)but there are still too many bridges in SOIC glued to the bottom of PCB. Why?

    6.  Pads are designed correctly for a chip component but one fillet is good and the other one is not.  What is the most likely cause?

    7.  You were having good results in the morning but when you come back after lunch, there are too many solder balls on the board. What happened?

    8.  A BGA joint is designed with NSMD bottom on the PCB side but with SMD pad on the package side? Where would you expect the failure to happen first? Why?

    9.  The laminate you have been using all this time has been just fine but when you switched to Lead Free, you are seeing more field returns? Why?

    10.  What is the easiest solution to prevent corrosion of pads with immersion surface finish? Why some large users don’t do that?

    11.  What are the two consequences of reflow soldering parts with moisture in them? What would a practically no cost solution to prevent such a problem?

    12.  An ENIG surface finish board is failing and you think the cause is black pad due to poor process control at PCB supplier but the supplier suggests the cause to be something else like profile or ICT, how do you prove who is right?

    13.  What could be the potential cause of huge voids in BGAs? What are some other symptoms to confirm the root cause you are thinking?

    14.  What could cause oval shape of BGAs balls in x-Ray image and bulging appearance in side cross-sectional photos?

    15.  Head in Pillow became more common when your component supplier starting sending you very clean BGAs since he started cleaning to make sure there are no halogens on his parts.  Why?

    16.  Your printing process and profile are good but you are still having head in pillow problem. What do you do now?

    17.  True or False: Exposed copper when using OSP surface finish is more likely even if you use very aggressive water soluble flux commonly referred to as Organic Acid flux

    18.  The parts are being placed correctly by the pick and place machine but after reflow you see some misalignment but only in active devices and not in passive devices? What is the possible cause?

    19.  In your BGAs you are seeing bridging only in corner joints? What would be the cause?

    20.  Your lead free solder joints are not as shiny as they used to be in tin-lead assembly. What should you do?

    21.  What should be the ratio of bridge to opens in your product? How to achieve that ratio and why?

    22.  Your products meet DFM guidelines, your suppliers are providing parts as per the industry standard and you have the latest SMT equipment but your yield is still not very good and your boss is not very happy with product yield.. What do you tell her?

    23.  Toe fillets in BTC are not always feasible. True or False.  Why?

    24.  What is the void requirement for BGA? Is it different for BTC? Why?


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