SMT - End of an Era: Moore’s Law

Two cores are better than one. Why? Intel says so. It has to do with hitting the brick wall in Moore’s Law. And who would know better than Intel about it?

Moore’s Law is named after Gordon Moore, co-founder and the largest shareholder of the world’s largest chipmaker (and my former employer), Intel. The law states that numbers of transistors on silicon will double every 18 months. This phenomenon, which has been almost like clockwork every 18 months for the past 45 years, has made it possible to buy increasingly more powerful computers at lower prices. This is about to change.

On May 7, Intel announced that the company will abandon its long-held practice of ever-smaller and faster chips to introduce silicon that contains two engines working together to satisfy the multitasking demands of today’s multimedia center PCs. Therefore, we may have hit the long-awaited brick wall in Moore’s Law. This shift in direction is like changing from single-cylinder to multi-cylinder engines to achieve more horsepower, an abrupt change from the past practice of packing more transistors on an ever-smaller sliver of silicon, made possible by Moore’s Law.

Moore’s Law still holds true, but its reign may be ending soon. It has been predicted that Moore’s Law may end by the time we enter the age of 0.10 µm (100-nanometer or 100 billionth of a meter) silicon technology. Today, 0.09 µm or 90-nanometer technology is in high-volume production. At such close distances between conductors, insulating atoms between traces are not sufficient to differentiate between 0 and 1 (off or on) and current tends to leak to the insulating material, causing unintended shorts (off or on). Changing the architecture in silicon design with more cache memory on the chip and faster system bus speed will ensure better performance. Intel will no longer label its processors in terms of megahertz or gigahertz; instead, the company will change to a numbering system that takes into account all microprocessor performance. Intel will still work to shrink the size of silicon, but the benefit of this effort now has diminishing returns. Therefore, the company’s new direction essentially is to increase the size of the silicon by dividing up the functions of microprocessors in two independent sections, or cores, on the same chip. Each core will work together but perform different functions simultaneously. This is the current focus of Intel engineers in Hillsboro, Ore.

The new approach of doing two tasks in parallel may be only slightly faster than the old one of doing the same two tasks in series, but some added benefits come with this new approach. The heat generated is a function of voltage and speed. With the old approach, unless the silicon is adequately cooled, performance suffers. The new approach will be easier to cool while achieving higher performance. So when looking for your new computer, don’t look at processor speed alone but rather overall performance — a new numbering and rating system to be promoted by Intel.

In the meantime, we are not fully using silicon’s performance. For example, while the silicon designer is dealing with silicon’s performance issues in picoseconds, or trillionths of a second (10-12), the system designer is still struggling with performance issues in nanoseconds, or billionths of a second (10-9) on the motherboard. This 1,000X reduction in performance is caused by packages that house the silicon, commonly referred to as package parasitics. Package parasitics are the inductance and capacitance of lead wires outside the package and bond wires inside the package that get in the way of electrons. In addition, traces on the motherboard that connect different silicon packages slow the electron down even further. The challenge for engineers in component packaging, printed circuit board (PCB) and printed circuit assembly is: How to improve package and printed circuit performance to improve silicon performance?

Today the weakest link in the interconnection scheme is the substrate or the board. Traditional and widely used substrate fabrication technology cannot accommodate fine lines and microvias for interconnecting high pin count and lower pitch packages (or silicon). PCB assembly must take on the challenge to build boards with finer features and smaller vias cost effectively. In addition, the impending changeover to new process technology associated with lead-free soldering, which requires higher soldering temperatures will further compound this problem. The industry must accelerate its research efforts in substrate and package technologies to achieve higher performance, especially now that the era of Moore’s Law may be coming to an end.

With outsourcing the new mantra in assembly, there is practically no budget for packaging and assembly technologies. While progress in silicon technology is necessary, highest performance cannot be achieved within a poor package and circuit board industry. The Intels of the world should focus on packaging and board technologies to compensate for performance losses that will be felt due to the end of an era: Moore’s Law.
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