SMT Packaging Moore’s Law and You

Gordon Moore, whose name is synonymous with integrated circuit (IC) technology, retired from the Intel board this May. Dr. Moore was one of the original founders of Intel, which was founded in 1968. In 1965, Dr. Moore was preparing a speech and made a memorable observation. When he started graphing data about the growth in memory chip performance, he realized there was a striking trend. Each new chip contained roughly twice as much capacity as its predecessor, and each chip was released within 18 to 24 months of the previous chip. If this trend continued, he reasoned, computing power would rise exponentially over a relatively brief period of time.
Why is Moore’s Law so important for the average person? The cost of a transistor has gone down some ten million fold in last 40 years or so. No other industry has made a similar cost improvement, particularly in such a short time.
The major reason for this is what Dr. Moore considers the violation of Murphy’s Law. By making things smaller, everything gets better simultaneously. The performance goes up. We can make more reliable systems. But most importantly, the cost of an individual transistor drops dramatically. Essentially, we can pack more in a given area on the silicon. We sell real estate, and the more we can put in a given micro-acre, the lower the cost of the electronics.
Moore’s Law described a trend that still remains remarkably accurate. However, people have been wondering when Moore’s law is going to hit a brick wall. The concern becomes a reality in the age of 0.10 µ technology because the insulating atoms between traces are not sufficient to differentiate between 0 and 1 (off or on). At such ultra-fine features in silicon, the electron may punch through the insulating material, causing an unintended short. Currently, at companies such as Intel, silicon technology is at 0.13 µ. Using today’s deep ultraviolet lithography technique, circuits can be printed as small as 0.10 µ. Because 0.13 µ technology already is under production, a 0.10 µ limit can be reached during 2004 to 2005. The problem is that images cannot be made much smaller than the wavelength of the light used to make the image. Fundamental physics limits this. So what is going to happen after that?
There are people and programs working to address the material and process issues to keep Moore’s Law alive. And one of those programs is a $250 million partnership between the Department of Energy and the U.S. semiconductor industry. This partnership was set up in September 1997 and was funded completely by private companies. As planned, the consortium’s work has been very much on track. Last month, the consortium led by Intel announced that it has produced a prototype machine using a process called extreme ultraviolet (EUV) lithography. This machine reduces features on silicon to 0.03 µ. Using this machine, Moore’s Law will continue holding at least until 2010.
The light wave’s length is key to the consortium’s new technology. Because the EUV light has a shorter wavelength, smaller features can be etched into silicon. But the invisible light poses some new challenges. It can be absorbed by both air and the lenses used. Therefore, the process is used in vacuum and mirrors focus the light. The question is not whether but when EUV lithography will be in production. The technology is expected to be transferred to consortium members such as Intel, AMD and Motorola by 2005.
The semiconductor industry is pooling their resources to solve a common problem. Once that is accomplished, the individual members will implement the technology to compete in the market place.
Keep in mind that while silicon designers are doing everything possible, they are not the only ones who can keep Moore’s Law alive. The packaging engineers can, as well. For example, while the silicon designer is dealing with silicon’s performance issues in picoseconds (10-12), the system designer still struggles with performance issues in nanoseconds (10-9) on the motherboard. This 1,000X performance reduction is caused by the packages that house the silicon — commonly referred to as package parasitics. They are undesired lead (outside the package) and bond wire (inside the package) inductance and capacitance that get in the way of electrons trying to quickly reach their destinations.
Additionally, motherboard traces that connect different silicon packages slow the electron down even further. The challenge for engineers in component packaging and printed circuit assembly (PCA) lies in enhancing package and printed circuit board (PCB) performance to improve silicon performance.
Packages perform some very important functions, e.g., providing power to the silicon and keeping it cool. If heat is not adequately dissipated, the higher junction temperature will slow the electrons. In a way, packages make it possible to speed things up. If the packages do not keep the silicon cool, the computer box designer must use various heat sinks and come up with ways to keep air moving without making the computer noisy. Packages also make it possible to interconnect the signals of all the silicon on the motherboard, enabling the electrons to talk to each other. Materials used in making the PCB (e.g., the material’s dielectric constant), and the size and type of vias used for interconnection, play important roles in silicon performance.
To achieve the highest performance, the package must be deleted and bare silicon must be used. But that will not be easy for the engineers who deal with mounting bare silicon on motherboards. The terms used for mounting bare silicon are chip-on-board (COB), flip chip and direct chip attach (DCA). Each term represents a different process. COB is used when the silicon is either wire bonded to the board directly or is used in the form of tape-automated bonding (TAB). However, chip, wire and TAB add wire-bond inductance similar to the package. Highest performance is achieved when the bare silicon is flipped directly over and bonded to the underlying substrate. No wire bonds or leads are involved in the flip chip process.
One can achieve higher performance with bare chips, but a new problem is created. The packages allow silicon pretesting before soldering to the board. Of all multiple chips on the board, it takes only one bad piece of silicon to render the entire assembly worthless. To correct the problem, the bad silicon must be removed and replaced. Bare silicon rework on a substrate is very difficult and expensive. On the other hand, if the silicon is housed in a package, the test sockets and the whole burn-in and test infrastructure is in place to enable the use of functional silicon only. If significant progress is made in bare silicon testing, higher performance can be harnessed from existing silicon.
This issue of not being able to test bare silicon is referred to as the known good die (KGD) problem. Although the industry has made progress in this area, it is not easy to test a bare die. If the silicon is housed in a package (or used as a TAB device), the problem of using bad silicon does not arise. If using bare silicon achieves the needed performance, you must be willing to accept a higher number of rejects because of the KGD problem. If you are willing, it is possible to achieve higher performance. There are applications — for example, niche applications such as multichip modules (MCM) — where it is worthwhile to pay to achieve the needed performance.
The solution for the industry may not necessarily be getting rid of the package, but developing more efficient packages that can perform the traditional functions — protecting, powering, interconnecting and providing KGD — without significant performance penalty.
As noted in my previous columns, the weakest link in the interconnection scheme is the substrate or board. Traditional and widely used substrate fabrication technology cannot accommodate the fine lines and microvias needed for interconnecting high-pin count and lower pitch packages (or silicon). The PCB assembly industry will have to build boards with finer features and smaller vias in a cost-effective manner. We must think about really building “printed” circuit boards. As we know, there is nothing “printed” in current printed circuits; the copper is etched to make the circuit. The industry must move on to additive processes by printing finer features on the PCB.

While package technology has not made progress comparable to silicon technology, substrate technology is in its “horse and buggy days” compared to package technology (although recent progress in microvia technology is very encouraging). Unless the industry progresses in substrate and package technologies, achieving performance in the picoseconds will remain only a dream.

Fortunately, there are some companies that have developed photopolymerization process for the preparation of high quality, electronically conducting organic polymer films that can be used to add lines as narrow as 10 µ. If you would like some specific details, you can send me an email. This is a real progress since the current state of the art in PCB manufacturing is 250 µ. But such technologies need additional development effort to make them cost effective in high volume production.

Where does the industry go from here? If you look at research and development (R&D) budgets and efforts spent on the packaging and PCB industries vs. the silicon industry, there is no comparison. All the dollars are going into silicon development. The $250 million dollar consortium effort mentioned above is an example. Progress in silicon technology is needed, but peak performance with a poor package and PCB cannot be achieved. The weakest link in the chain will determine the ultimate performance. It is critical that R&D budgets for board fabrication and assembly technologies receive adequate attention from the silicon industry. Another industry consortium funded by PCB and semiconductor companies is needed to keep the United States on the leading edge, and to keep Moore’s law alive for the foreseeable future.

RAY P. PRASAD is an SMT Editorial Advisory Board member and author of the textbook Surface Mount Technology: Principles and Practice. Additionally, he is president of BeamWorks Inc. (, a supplier of selective automated assembly systems, located in Portland, OR and founder of the Ray Prasad Consultancy Group, which specializes in helping companies establish strong internal SMT infrastructure. Contact him at P.O. Box 219179, Portland, OR 97225; (503) 297-5898 or (503) 646-3224; Fax: (503) 297-0330; Web site:
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