SMT - Role of Packaging in Moore's Law

I was having a leisurely morning reading my Saturday New York Times not hoping to find any thing that important. Then I saw the front-page article " Chip Progress Forecast to Hit A Big Barrier" with tag line Scientists Seeing Limits to Miniaturization (New York Times, October 9, 1999). I thought, hey, the silicon engineers are not the only ones who can help keeping Moor’s Law alive. Engineers who find ways to house and interconnect the silicon with other silicon on the motherboard have a tremendous opportunity to harness the full potential of silicon. Before I go into what the packaging engineers can do to alleviate some of silicon’s performance, let me briefly discuss the potential problems with Moore’s Law.

People have been wondering for sometime as to when Moore’s Law may hit a brick wall. Moore’s Law, even though not a physical law, is named after legendary Gordon Moore, cofounder of world’s largest chip maker (and my former employer) has been amazingly true for the last 40 years. It states that number of transistors on a silicon will double every 18 months. The original law stated that silicon’s performance would double every two years. It was later changed to 18 months since progress in silicon technology was happening even faster than Dr. Moore originally thought. Doubling of silicon’s performance almost like clock work every 18 months has made it possible to buy more and more powerful computers at lower and lower prices. Computers and servers – large and small, are the building blocks of Internet. And we can all agree that Internet has changed our lives – some bad but mostly good. Good or bad there is no turning back.

Moore’s law still holds true but it rein may be ending soon. This view is expressed by no other than a scientist from Intel - Paul Packman. In the September 26, 1999 issue of Science, Packman warns that in couple of years Moore’s Law may end unless some fundamental change in technology takes place. The concern becomes almost real once we enter the age of 0.10 micron technology because the insulating atoms between traces are not sufficient to differentiate between 0 and 1 (off or on). At such ultra fine features in silicon, the electron may punch through the insulating material and thus causing unintended short (off or on). Currently the silicon technology is at 0.18 micron. In a year or two the industry will move to 0.13 micron and within four years to 0.10 micron. So we are not too far away from the Chicken Little’s sky is falling scenario. Packman is not alone in his view. He is joined by leading scientists from IBM and other companies. You can also be sure that there are people who are working on addressing the material and process issues to keep the Moore’s Law alive. So there are many things that silicon designers and process engineers are working on to prevent electron tunneling. In the mean time what can the Packaging engineers do?

We should remember that we are not using current silicon’s performance fully. For example, while the silicon designer is dealing with silicon’s performance issues in picoseconds (10-12), the system designer is still struggling with performance issues in nanoseconds (10-9) on the motherboard. This 1000X reduction in performance is caused by packages that house the silicon - commonly referred to as package parasitics. Package parasitics are those undesired lead (outside the package) and bond wires (inside the package) inductance and capacitance that get in the way of the electrons trying to get to their destinations fast. In addition, the traces on the motherboard that connect different silicon packages slow the electron down even further. So here lies the challenge for engineers in Component Packaging, Printed Circuit Board and Printed Circuit Assembly. How to improve package and printed circuit performance in order to improve silicon’s performance?

We need to keep in mind that packages perform some very important functions. For example, packages provide power to the silicon and keep them cool. If the heat is not dissipated adequately, the higher junction temperature (temperature of silicon) will slow the electrons down. So in a way the packages make it possible to speed things up. If the packages don’t keep the silicon cool, the computer box designer has to use various types of heat sinks and come up with ways to keep air moving without making the computer noisy. Packages also make it possible to interconnect the signals of all the silicon on the motherboard so that the electrons can all talk to each other. And the type of materials used in making the circuit board (the dielectric constant of the material) and the size and types of vias used for interconnection plays an important role in silicon’s performance.

To achieve the highest performance, we have to get rid of the package by using bare silicon. But that won’t be easy for the engineers who have to deal with manufacturing issues of mounting bare silicon on motherboard. The terminology used for mounting bare silicon is chip on board, flip chip, and direct chip attach. There are some real differences in these terms. The chip on board term is used when the silicon is either wire bonded to the board directly or is used in the form of TAB (tape automated bonding). However, chip and wire and TAB do add the wire bond inductance almost like the package. The highest performance is achieved when the bare silicon is directly flipped over and bonded to the underlying substrate. No wire bonds or leads are involved in the flip chip process.

One can achieve a higher performance with bare chips but you create one major new problem. The packages allow pre-testing of silicon before being soldered to the board. Out of all the multiple chips on the board, it takes only one bad silicon to render the entire assembly worthless. To correct the problem, you have to remove and replace the bad silicon. And rework of bare silicon on a substrate is almost impossible and very difficult and expensive to say the least. One the other hand if the silicon is housed in a package, the test sockets and the whole burn-in and test infrastructure is in place to enable use of only functional silicon. So if we can make significant progress in the bare testing of silicon, we can harness higher performance from the existing silicon.

This issue of not being able to test bare silicon is referred to as KGD (known good die) problem. It is not easy to test a bare die although industry has good progress in this area. If that silicon is housed in a package (or used as a TAB device), the problem of using bad silicon does not arise. So if you insist on using the bare silicon to achieve the performance you need, you can use flip chip but must be willing to pay higher cost in terms of higher rejects due to KGD problem. So it is possible to achieve higher performance if one is willing to pay higher cost. There are certainly applications where it is worthwhile to pay higher cost to achieve the needed performance. But it is generally in niche applications such as multichip modules (MCM).

The solution for the industry may not be necessarily in getting rid of the package but developing more efficient packages that can perform the traditional function of the package of protecting, powering, interconnecting and providing KGD without significant penalty in performance.

The weakest link in the interconnection scheme is the substrate or the board. The traditional and widely used substrate fabrication technology cannot accommodate fine lines and microvias needed for interconnecting high pin count and lower pitch packages (or silicon). The printed circuit board assembly will have to take the challenge to build boards with finer features and smaller vias in a cost-effective way.

While package technology has not made the comparable progress achieved in the silicon technology over the last decade, the substrate technology is in the horse and buggy days compared to package technology, although recent progress in micro-via technology is very encouraging. Unless the industry makes comparable progress in substrate and package technologies, the desire of achieving performance in the pico seconds will remain only a dream.

So where do we go from here? If you look at the R&D budget and effort on package and printed circuit board industry versus silicon industry, there is no comparison. All the dollars are going into silicon development. We certainly need that progress in silicon technology but you cannot achieve the highest performance with a poor package and circuit board industry. The weakest link in the chain will determine the ultimate performance. So it is critical that R&D budgets of packaging including board fabrication and assembly technologies get adequate attention by the silicon industry to keep the Moore’s Law alive for at least another 40 years.
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